论文标题
TSN的容错多阶段开关体系结构的分析
Analysis of Fault Tolerant Multi-stage Switch Architecture for TSN
论文作者
论文摘要
我们进行了可行性分析，用于利用高度可用的多阶段架构，用于用于在有限的潜伏期内而不是传统的单阶段体系结构内发送高优先级，关键任务流量的TSN开关。为了验证TSN功能，我们实现了“严格的优先级”功能。我们评估了两种架构在多个参数上的性能，例如容错，数据包延迟，吞吐量，可靠性，路径长度效率和每单位成本。容错分析表明，多阶段架构比单阶段更好。多阶段体系结构的平均延迟和吞吐量虽然低，但可以认为与单级同行相当。但是，多阶段体系结构无法满足单阶段体系结构在可靠性，路径长度效率和成本效益等参数上的性能。改善的容错性是以增加硬件资源，成本和复杂性的成本为代价。但是，随着硬件设计和高效体系结构设计中具有成本效益的技术的出现，基于多阶段的基于架构的TSN开关可以与单级交换机TSN开关相当可比。这项工作使最初的信心是，可以针对需要确定性和可靠性在关键信息的交流中进一步追求多阶段架构。
We conducted the feasibility analysis of utilizing a highly available multi-stage architecture for TSN switches used for sending high priority, mission-critical traffic within a bounded latency instead of traditional single-stage architectures. To verify the TSN functionality, we implemented the 'strict priority' feature. We evaluated the performance of both architectures on multiple parameters such as fault tolerance, packet latency, throughput, reliability, path length effectiveness, and cost per unit. The fault tolerance analysis demonstrated that the multi-stage architecture fairs better than the single-stage counterpart. The average latency and throughput performance of multi-stage architectures, although low, can be considered comparable with single-stage counterparts. However, the multi-stage architecture fails to meet the performance of single-stage architectures on parameters such as reliability, path length effectiveness, and cost-effectiveness. The improved fault tolerance comes at the cost of increased hardware resources, cost, and complexity. However, with the advent of cost-effective technologies in hardware design and efficient architecture designs, the multi-stage switching architecture-based TSN switches can be made reasonably comparable to single-stage switching TSN switches. This work gives initial confidence that the multi-stage architecture can be pursued further for safety-critical systems that require determinism and reliability in the communication of critical messages.
