论文标题
与HLS生成的加速器的自行车的硬件软件共同设计
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators
论文作者
论文摘要
为了减轻量子计算机的安全威胁，NIST正在进行一个过程来标准化后量子加密系统，旨在评估其安全性并加快其在生产场景中的采用。为每个候选人提出了几种硬件和软件实现，而只有几个具有CPU和FPGA的目标异质平台。这项工作为嵌入式平台提供了自行车的HW/SW共同设计，该平台具有CPU和小型FPGA，并采用高级合成（HLS）来及时提供硬件加速器。与针对性能优化HLS加速器的最新解决方案相反，提出的解决方案针对嵌入式系统中异质平台中实现的小型FPGA。与自行车的仅软件执行相比，在整个Xilinx Zynq-7000家族的芯片上收集的实验结果突出了从Z-7010上的1.37倍到2.78倍到Z-7020上的2.78倍的性能加速。
In order to mitigate the security threat of quantum computers, NIST is undertaking a process to standardize post-quantum cryptosystems, aiming to assess their security and speed up their adoption in production scenarios. Several hardware and software implementations have been proposed for each candidate, while only a few target heterogeneous platforms featuring CPUs and FPGAs. This work presents a HW/SW co-design of BIKE for embedded platforms featuring both CPUs and small FPGAs and employs high-level synthesis (HLS) to timely deliver the hardware accelerators. In contrast to state-of-the-art solutions targeting performance-optimized HLS accelerators, the proposed solution targets the small FPGAs implemented in the heterogeneous platforms for embedded systems. Compared to the software-only execution of BIKE, the experimental results collected on the systems-on-chip of the entire Xilinx Zynq-7000 family highlight a performance speedup ranging from 1.37x, on Z-7010, to 2.78x, on Z-7020.
