论文标题
基于FPGA的高分辨率TDL TDCS的低死时间，有效的资源编码方法
A low dead time, resource efficient encoding method for FPGA based high-resolution TDL TDCs
论文作者
论文摘要
本文提出了一种新颖的编码方法，用于绘制延迟线（TDL）数字转换器（TDC）的精细时间数据。它基于划分和争夺策略，其优势是显着降低了逻辑资源的利用，同时保留了低死时间的性能。此外，可以通过这种方法解决高级设备中高气泡深度的问题。证明了四个示例，这些示例是在Xilinx Artix-7场地可编程阵列（FPGA）设备中实现的，并且本文中介绍的编码方法用于编码正常TDL TDC，半长度延迟线TDC的罚款时间数据，以及双层延迟线TDC，以及双层边缘和四范围和四范围的Wave Wave Union TDCS。与采用传统编码器的最新发表论文的TDC相比，本文中TDC的逻辑利用率在不同情况下减少了45％至70％，而在一个时钟周期中可以限制编码的死时间。还获得了所证明的TDC的可接受分辨率，证明了编码方法的功能。
This paper presents a novel encoding method for fine time data of a tapped delay line (TDL) time-to-digital Converter (TDC). It is based on divide-and-conquer strategy, and has the advantage of significantly reducing logic resource utilization while retaining low dead-time performance. Furthermore, the problem of high bubble depth in advanced devices can be resolved with this method. Four examples are demonstrated, which were implemented in a Xilinx Artix-7 Field Programmable Gate Array (FPGA) device, and encoding method presented in this paper was employed to encode fine time data for normal TDL TDC, a half-length delay line TDC, and double-edge and four-edge wave union TDCs. Compared with TDCs from the latest published papers that adopt traditional encoders, the logic utilization of TDCs in this paper were reduced by a factor of 45% to 70% in different situations, while the encoding dead time can be restricted in one clock cycle. Acceptable resolutions of the demonstrated TDCs were also obtained, proving the functionality of the encoding method.
