论文标题
基于HZO的Ferronems Mac用于内存计算
HZO-based FerroNEMS MAC for In-Memory Computing
论文作者
论文摘要
本文展示了基于HAFNIUM氧化锆(HZO)基于铁电的非象征,作为非常低的能力电容式读数内存计算的基本构建块。报告的设备由250美元$ $ m $ \ times $ 30 $ $ m unimorph Cantilever和20 nm厚的铁电厚的hzo hzo上的1 $ $ $ m $ m $ m $ sio_2 $ .partial铁电交换hzo中的hzo hzo hzo hzo Analog可编程控制量的计算量($)乘以(MAC)操作。通过用不同的输入电压$ v_ {in} $来操作设备,记录了压电Unimorph的位移。结果位移是根据铁电编程/极点电压$ v_p $的函数测量的。中央梁位移的斜率($δ_{max} $)vs $ v_ {in} $在182.9nm/v(对于-8 $ v_p $)和-90.5nm/v(用于8 $ v_p $)之间,表明$ v_p $可用于改变运动方向的方向。 AC致动的结果($δ_{max} $)在-18至36 nm的范围内,是输入电压和编程的$ d_ {31} $的缩放产物(由$ v_p $约束)。乘法函数是具有铁电Nems Unimorph的MAC操作的基本单元。可以通过求和电容变化,提供实现多输入和多重神经元的途径来添加许多此类梁的位移。缩放和制造分析表明,该设备可以兼容CMO,从而实现高内存计算吞吐量。
This paper demonstrates a hafnium zirconium oxide (HZO)-based ferroelectric NEMS unimorph as the fundamental building block for very low-energy capacitive readout in-memory computing. The reported device consists of a 250 $μ$m $\times$ 30 $μ$m unimorph cantilever with 20 nm thick ferroelectric HZO on 1 $μ$m $SiO_2$.Partial ferroelectric switching in HZO achieves analog programmable control of the piezoelectric coefficient ($d_{31}$) which serves as the computational weight for multiply-accumulate (MAC) operations. The displacement of the piezoelectric unimorph was recorded by actuating the device with different input voltages $V_{in}$. The resulting displacement was measured as a function of the ferroelectric programming/poling voltage $V_p$. The slopes of central beam displacement ($δ_{max}$) vs $V_{in}$ were measured to be between 182.9nm/V (for -8 $V_p$) and -90.5nm/V (for 8 $V_p$), demonstrating that $V_p$ can be used to change the direction of motion of the beam. The resultant ($δ_{max}$) from AC actuation is in the range of -18 to 36 nm and is a scaled product of the input voltage and programmed $d_{31}$ (governed by the $V_p$). The multiplication function serves as the fundamental unit for MAC operations with the ferroelectric NEMS unimorph. The displacement from many such beams can be added by summing the capacitance changes, providing a pathway to implement a multi-input and multi-weight neuron. A scaling and fabrication analysis suggests that this device can be CMOS compatible, achieving high in-memory computational throughput.