论文标题
迈向低S型1024梁数字阵列:32梁子系统5.8 GHz
Towards a Low-SWaP 1024-beam Digital Array: A 32-beam Sub-system at 5.8 GHz
论文作者
论文摘要
毫米波通信需要多束光束形成,以便利用遭受障碍物,路径损失和多路径效应的无线通道。与模拟分阶段阵列相比,数字多束光束形成具有最大的自由度。但是,电路的复杂性和功耗是数字多冰系统的重要限制。为无乘法的32点线性变换提出了低复杂性数字计算体系结构,该变换近似于多个同时的RF梁,类似于离散的傅立叶变换(DFT)。由于$ \ Mathcal {o}(n \:\ log n)$的FFT复杂性,DFT实现的算术复杂性降低了,降低到零,从而分别减少芯片区域和动态功耗的46%和55%。本文描述了使用2D阵列靶向1024梁的32点DFT近似值,并显示了无乘数近似值及其映射到32束束子系统,该系统由5.8 GHz天线组成,该系统可用于生成1024个数字梁而无需乘法的1024个数字光束。使用Xilinx FPGA以120 MHz的带宽为单位,实现实时光束计算。将理论束性能与来自固定点FFT以及提议的无乘数算法的测得的RF模式进行了比较,并且非常一致。
Millimeter wave communications require multibeam beamforming in order to utilize wireless channels that suffer from obstructions, path loss, and multi-path effects. Digital multibeam beamforming has maximum degrees of freedom compared to analog phased arrays. However, circuit complexity and power consumption are important constraints for digital multibeam systems. A low-complexity digital computing architecture is proposed for a multiplication-free 32-point linear transform that approximates multiple simultaneous RF beams similar to a discrete Fourier transform (DFT). Arithmetic complexity due to multiplication is reduced from the FFT complexity of $\mathcal{O}(N\: \log N)$ for DFT realizations, down to zero, thus yielding a 46% and 55% reduction in chip area and dynamic power consumption, respectively, for the $N=32$ case considered. The paper describes the proposed 32-point DFT approximation targeting a 1024-beams using a 2D array, and shows the multiplierless approximation and its mapping to a 32-beam sub-system consisting of 5.8 GHz antennas that can be used for generating 1024 digital beams without multiplications. Real-time beam computation is achieved using a Xilinx FPGA at 120 MHz bandwidth per beam. Theoretical beam performance is compared with measured RF patterns from both a fixed-point FFT as well as the proposed multiplier-free algorithm and are in good agreement.