论文标题
具有标准单元格的有效量子电路设计，并应用于中性原子量子计算机
Efficient Quantum Circuit Design with a Standard Cell Approach, with an Application to Neutral Atom Quantum Computers
论文作者
论文摘要
我们通过使用从经典电路设计借用的标准电池方法来设计量子电路，该电路可以加速使用常规结构的电路布局。我们的标准单元是一般的，可用于所有类型的量子电路：错误校正与否。标准单元格方法可以制定布局感知路由算法。我们的方法直接适用于支持量子班的中性原子量子计算机。这样的计算机可以为内存，处理和测量启用分区体系结构，并使用量子存储（内存和测量区）和标准单元（处理区）设计电路。本文中，我们将立方标准单元用于Toffoli大门，从3D体系结构开始，我们设计了一个乘法电路。我们提供了证据表明，与自动路由方法相比，我们的布局意识路由器的速度明显更快，并实现了较浅的3D电路（至少为2.5倍），并且路由成本较低。此外，我们的共同设计方法可用于估计量子计算所需的资源，而无需使用复杂的汇编方法。我们得出的结论是，在布局感知的路由的支持下，标准单元为量子电路编译的非常大规模的方法铺平了道路。
We design quantum circuits by using the standard cell approach borrowed from classical circuit design, which can speed-up the layout of circuits with a regular structure. Our standard cells are general and can be used for all types of quantum circuits: error-corrected or not. The standard cell approach enables the formulation of layout-aware routing algorithms. Our method is directly applicable to neutral atom quantum computers supporting qubit shuttling. Such computers enable zoned architectures for memory, processing and measurement, and we design circuits using qubit storages (memory and measurement zones) and standard cells (processing zones). Herein, we use cubic standard cells for Toffoli gates and, starting from a 3D architecture, we design a multiplication circuit. We present evidence that, when compared with automatic routing methods, our layout-aware routers are significantly faster and achieve shallower 3D circuits (by at least 2.5x) and with a lower routing cost. Additionally, our co-design approach can be used to estimate the resources necessary for a quantum computation without using complex compilation methods. We conclude that standard cells, with the support of layout-aware routing, pave the way to very large scale methods for quantum circuit compilation.
