论文标题
高度非线性和障碍电子设备的建模缺陷级切换
Modeling Defect-Level Switching for Highly-Nonlinear and Hysteretic Electronic Devices
论文作者
论文摘要
以前，我们证明了基于电荷陷阱和在不动的亚稳态缺陷处的电荷陷阱和脱落的两端电子设备中电阻率的持续变化[H. Yin，A。Kumar，J.M。Lebeau和R. Jaramillo，物理。修订版应用15，014014（2021）];我们将这些设备称为缺陷级开关（DLS）设备。 DLS设备具有全电子电阻开关，因此由于电压时间困境而挥发。但是，挥发性电阻开关的动力学对于新兴应用程序（例如跨点存储器中的选择器和神经形态计算概念）可能很有价值。为了使用这些挥发性电阻开关设计内存和计算电路，准确的建模至关重要。在这项工作中，我们开发了一个准确的分析模型，以基于CU（IN，GA）SE2（CIGS）和II-VI半导体的点缺陷亚稳定性的既定理论来描述DLS设备中的开关物理。我们模型的分析性质允许对DLS设备的动态行为进行及时的模拟。我们对设置和重置编程脉冲的持续时间进行建模，相对于脉冲振幅，可以将其缩短。我们还证明了反设计的概念：给定所需的电阻状态，可以相应地选择编程信号的宽度和幅度。
Previously, we demonstrated hysteretic and persistent changes of resistivity in two-terminal electronic devices based on charge trapping and detrapping at immobile metastable defects [H. Yin, A. Kumar, J.M. LeBeau, and R. Jaramillo, Phys. Rev. Applied 15, 014014 (2021)]; we termed these devices as defect-level switching (DLS) devices. DLS devices feature all-electronic resistive switching and thus are volatile because of the voltage-time dilemma. However, the dynamics of volatile resistive switches may be valuable for emerging applications such as selectors in crosspoint memory, and neuromorphic computing concepts. To design memory and computing circuits using these volatile resistive switches, accurate modeling is essential. In this work we develop an accurate and analytical model to describe the switching physics in DLS devices, based on the established theories of point defect metastability in Cu(In,Ga)Se2 (CIGS) and II-VI semiconductors. The analytical nature of our model allows for time-efficient simulations of dynamic behavior of DLS devices. We model the time durations of SET and RESET programming pulses, which can be exponentially shortened with respect to the pulse amplitude. We also demonstrate the concept of inverse design: given desired resistance states, the width and amplitude of the programming signal can be chosen accordingly.
