论文标题
延迟线的可寻址超导体集成电路内存
Addressable Superconductor Integrated Circuit Memory from Delay Lines
论文作者
论文摘要
逻辑方案和制造过程的最新进展使人们对使用超导电子电子设备进行节能计算和量子控制处理器有了重新兴趣。但是，可扩展的超导内存仍然构成挑战。为了解决这个问题，我们提出了一种方法，可以通过利用超导被动传输线的最小衰减和分散性能来开发延迟线记忆系统，从而仅强调储物单元小型化。这种完整的超导设计以20 GHz至100 GHz之间的速度运行，$ \ pm $ 24 \％和$ \ pm $ 13 \％偏差利润率，并在MBIT/CM $ $^2 $的10s中演示了MIT Lincoln Lincoln Laincoln Laboratory SC2制造工艺中的数据密度。此外，该设计的循环性质允许最小的控制电路，消除了对数据分裂和合并的需求，并实现了连续访问和可调地理记忆的廉价实现。制造过程的进一步进步表明，数据密度为100 mbit/cm $^2 $及以后
Recent advances in logic schemes and fabrication processes have renewed interest in using superconductor electronics for energy-efficient computing and quantum control processors. However, scalable superconducting memory still poses a challenge. To address this issue, we present an alternative to approaches that solely emphasize storage cell miniaturization by exploiting the minimal attenuation and dispersion properties of superconducting passive transmission lines to develop a delay-line memory system. This fully superconducting design operates at speeds between 20 GHz and 100 GHz, with $\pm$24\% and $\pm$13\% bias margins, respectively, and demonstrates data densities in the 10s of Mbit/cm$^2$ with the MIT Lincoln Laboratory SC2 fabrication process. Additionally, the circulating nature of this design allows for minimal control circuitry, eliminates the need for data splitting and merging, and enables inexpensive implementations of sequential access and content-addressable memories. Further advances in fabrication processes suggest data densities of 100s of Mbit/cm$^2$ and beyond
