论文标题
用于机器学习的过程，偏见和温度可伸缩的CMOS模拟计算电路
Process, Bias and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning
论文作者
论文摘要
与数字计算相比，模拟计算具有吸引力，因为它可以达到更高的计算密度和更高的能源效率。但是，与数字电路不同，由于晶体管偏见偏差，温度变化和有限的动态范围的差异，传统的模拟计算电路不能轻易地在不同的过程节点上映射。在这项工作中，我们概括了先前报道的基于边缘传播的模拟计算框架，用于设计新颖的\ textit {基于Shape的模拟计算}（S-AC）电路，这些电路可以很容易地在不同的过程节点上交叉映射。与数字设计类似的S-AC设计也可以缩放以获得精确，速度和功率。作为概念验证，我们展示了实现机器学习（ML）架构中通常使用的数学功能的S-AC电路的几个示例。使用电路模拟，我们证明了电路输入/输出特性从平面CMOS 180NM工艺到FinFET 7NM过程时保持稳健。此外，使用基准数据集，我们证明了基于S-AC的神经网络的分类准确性在两个过程中映射到温度变化时仍然坚固。
Analog computing is attractive compared to digital computing due to its potential for achieving higher computational density and higher energy efficiency. However, unlike digital circuits, conventional analog computing circuits cannot be easily mapped across different process nodes due to differences in transistor biasing regimes, temperature variations and limited dynamic range. In this work, we generalize the previously reported margin-propagation-based analog computing framework for designing novel \textit{shape-based analog computing} (S-AC) circuits that can be easily cross-mapped across different process nodes. Similar to digital designs S-AC designs can also be scaled for precision, speed, and power. As a proof-of-concept, we show several examples of S-AC circuits implementing mathematical functions that are commonly used in machine learning (ML) architectures. Using circuit simulations we demonstrate that the circuit input/output characteristics remain robust when mapped from a planar CMOS 180nm process to a FinFET 7nm process. Also, using benchmark datasets we demonstrate that the classification accuracy of a S-AC based neural network remains robust when mapped across the two processes and to changes in temperature.
