论文标题
PCB系统上实现DDR3内存界面的挑战：将DDR3 SDRAM DIMM连接到FPGA的方法
Challenges in implementing DDR3 memory interface on PCB systems: a methodology for interfacing DDR3 SDRAM DIMM to an FPGA
论文作者
论文摘要
毫无疑问，每位更快，更大和更低的功率，但是您如何将DDR3 SDRAM DIMM连接到FPGA？ DDR3标准解决了每位需求更快，更多的带宽和更低的功率，但是除了DDR2 ODT，SLEW速率降低速率等引入的挑战外，它还引入了新的设计挑战。DDR3fly-by-by topology需求意味着设计DDR3记忆的客户现在必须在PCB上进行写入并读取de-skew。本文将涵盖满足JEDEC定义的终止所需的建模，模拟和物理布局方法，并在PCB系统上设计DDR3内存接口所需的紧密计时要求。
Undoubtedly faster, larger and lower power per bit, but just how do you go about interfacing a DDR3 SDRAM DIMM to an FPGA? The DDR3 standard addresses the faster, more bandwidth and lower power per bit need, but it introduces new design challenges in addition to challenges introduced by DDR2 ODT, slew rate derating, etc. The DDR3 fly-by topology requirement means customers designing DDR3 memories must now account for write leveling and read de-skew on the PCB. This paper will cover modeling, simulation, and physical layout approaches required to meet JEDEC-defined termination and tight timing requirements for designing DDR3 memory interfaces on PCB systems.
