论文标题
优化量子读取的内存电路
Optimization of Quantum Read-Only Memory Circuits
论文作者
论文摘要
量子计算是一个快速扩展的字段,其应用程序从优化一直到复杂的机器学习任务不等。量子记忆虽然缺乏实用的量子计算机,但具有带来量子优势的潜力。例如,在量子机学习应用程序中,量子内存可以简化数据加载过程并可能加速学习任务。量子存储器还可以存储可重复使用以进行计算的中间量子状态。然而,量子记忆的深度,门计数和汇编时间,例如,量子仅读取记忆(QROM)尺度,地址线的数量使它们在最新的噪声中间尺度量子(NISQ)计算机中不切实际,超过4位地址。在本文中,我们提出了诸如定制逻辑和量子重置的技术,以减少QROM电路的深度和门计数,以靶向更广泛的地址范围,例如8位。与只有36%的Qubit开销相比,提出的方法将门和深度计数的数量减少至少2倍。观察到,最大成本为2.28倍乘以开销的成本,电路深度和门数的降低高达75倍,并减少了85倍的汇编时间。在实验上,与现有优化方法相比,在降低的错误率下,与现有优化方法相比,提出的预言电路的保真度也更高(高达73%,至40.8%)。
Quantum computing is a rapidly expanding field with applications ranging from optimization all the way to complex machine learning tasks. Quantum memories, while lacking in practical quantum computers, have the potential to bring quantum advantage. In quantum machine learning applications for example, a quantum memory can simplify the data loading process and potentially accelerate the learning task. Quantum memory can also store intermediate quantum state of qubits that can be reused for computation. However, the depth, gate count and compilation time of quantum memories such as, Quantum Read Only Memory (QROM) scale exponentially with the number of address lines making them impractical in state-of-the-art Noisy Intermediate-Scale Quantum (NISQ) computers beyond 4-bit addresses. In this paper, we propose techniques such as, predecoding logic and qubit reset to reduce the depth and gate count of QROM circuits to target wider address ranges such as, 8-bits. The proposed approach reduces the number of gates and depth count by at least 2X compared to the naive implementation at only 36% qubit overhead. A reduction in circuit depth and gate count as high as 75X and compilation time by 85X at the cost of a maximum of 2.28X qubit overhead is observed. Experimentally, the fidelity with the proposed predecoding circuit compared to existing optimization approach is also higher (as much as 73% compared to 40.8%) under reduced error rates.