论文标题
有选择性的偏置三末端垂直综合的回忆配置
Selectively biased tri-terminal vertically-integrated memristor configuration
论文作者
论文摘要
当回忆录用作电路中的电子组件时,可以为实施新型可重构电子设备提供机会。尽管它们已用于大型阵列,但对设备集合的研究相对有限。在这里,我们提出了带有共享中间电极的垂直堆叠的备忘录配置。我们研究了组合内部设备所呈现的复合电阻状态,并通过分别控制每个设备或通过更改完整配置来改变它们,该配置取决于中间浮动电极的选择性用法。共享的中部电极可以罕见地查看组合系统,该系统通常在垂直堆叠的设备中不可用。在这项研究的过程中,发现单个设备的单独切换将其效果延伸到完整的设备(尽管是非线性的),从而增加了电阻状态范围,从而导致更大数量的可区分状态(高于SNR方差限制),从而增强了设备的存储器。此外,通过将开关刺激应用于外部电极,可以同时切换两个设备,从而使整个配置具有带有单个回忆组件的电压分隔器。通过使用这种类型的配置并利用电压划分,可以使用浪涌保护脆弱的设备,同时发现可以同时重置堆叠的设备,从而大大降低了较大阵列中所需的重置时间。
Memristors, when utilized as electronic components in circuits, can offer opportunities for the implementation of novel reconfigurable electronics. While they have been used in large arrays, studies in ensembles of devices are comparatively limited. Here we propose a vertically stacked memristor configuration with a shared middle electrode. We study the compound resistive states presented by the combined in-series devices and we alter them either by controlling each device separately, or by altering the full configuration, which depends on selective usage of the middle floating electrode. The shared middle electrode enables a rare look into the combined system, which is not normally available in vertically stacked devices. In the course of this study it was found that separate switching of individual devices carries over its effects to the complete device (albeit non-linearly), enabling increased resistive state range, which leads to a larger number of distinguishable states (above SNR variance limits) and hence enhanced device memory. Additionally, by applying a switching stimulus to the external electrodes it is possible to switch both devices simultaneously, making the entire configuration a voltage divider with individual memristive components. Through usage of this type of configuration and by taking advantage of the voltage division, it is possible to surge-protect fragile devices, while it was also found that simultaneous reset of stacked devices is possible, significantly reducing the required reset time in larger arrays.