论文标题

IOTLB-SC:现代云系统中与加速器无关的泄漏源

IOTLB-SC: An Accelerator-Independent Leakage Source in Modern Cloud Systems

论文作者

Tiemann, Thore, Weissman, Zane, Eisenbarth, Thomas, Sunar, Berk

论文摘要

在服务器级计算中通常可以使用硬件外围设备(例如GPU和FPGA),以加速特定的计算任务,从数据库查询到机器学习。 CSP已将这些加速器集成到其基础架构中,并让租户根据其需求灵活地组合和配置这些组件。确保I/O界面对于确保在这些高度复杂,异构性但共享的服务器系统中,尤其是在云中的租户之间正确隔离,在云中,某些外围设备可能会受到恶意租户的控制。 在这项工作中,我们研究了将外围硬件组件彼此和系统的其余部分连接的接口。我们表明I/O内存管理单元(IOMMUS)(旨在确保外围设备的正确隔离)是新攻击表面的来源:I/O转换look -hoside -aside -aside hip -aside hubiDEside fold -aside buffer(iotlb)。我们表明,通过使用FPGA加速器卡,可以在IOTLB活动上获得精确的信息。该信息可用于掩盖外围设备之间的通信,而无需打扰CPU或直接从相邻加速的计算作业(例如GPU加速数据库)中提取泄漏。在通过CXL和PCIE 5.0引入细颗粒的通道之前,我们介绍了这种新发现的攻击表面的第一个定性和定量分析。此外,我们提出了可能的对策,软件开发人员,硬件设计人员和系统管理员可以用来抑制观察到的侧通道泄漏并分析其隐式成本。

Hardware peripherals such as GPUs and FPGAs are commonly available in server-grade computing to accelerate specific compute tasks, from database queries to machine learning. CSPs have integrated these accelerators into their infrastructure and let tenants combine and configure these components flexibly, based on their needs. Securing I/O interfaces is critical to ensure proper isolation between tenants in these highly complex, heterogeneous, yet shared server systems, especially in the cloud, where some peripherals may be under control of a malicious tenant. In this work, we investigate the interfaces that connect peripheral hardware components to each other and the rest of the system.We show that the I/O memory management units (IOMMUs) - intended to ensure proper isolation of peripherals - are the source of a new attack surface: the I/O translation look-aside buffer (IOTLB). We show that by using an FPGA accelerator card one can gain precise information over IOTLB activity. That information can be used for covert communication between peripherals without bothering CPU or to directly extract leakage from neighboring accelerated compute jobs such as GPU-accelerated databases. We present the first qualitative and quantitative analysis of this newly uncovered attack surface before fine-grained channels become widely viable with the introduction of CXL and PCIe 5.0. In addition, we propose possible countermeasures that software developers, hardware designers, and system administrators can use to suppress the observed side-channel leakages and analyze their implicit costs.

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