论文标题

放松时间超过0.1 ms

Path toward manufacturable superconducting qubits with relaxation times exceeding 0.1 ms

论文作者

Verjauw, J., Acharya, R., Van Damme, J., Ivanov, Ts., Lozano, D. Perez, Mohiyaddin, F. A., Wan, D., Jussot, J., Vadiraj, A. M., Mongillo, M., Heyns, M., Radu, I., Govoreanu, B., Potočnik, A.

论文摘要

随着超导量子平台在竞赛中朝着实用的量子计算机的越来越多的尺度逐渐成熟,由于缺乏过程控制而导致的量子不均匀性引起的限制变得显而易见。为了从行业规模的CMOS制造设施中的高级过程控制中受益,将需要不同的处理方法。尤其是,用于当前的最先进的量子台的双角度蒸发和提升技术通常与现代可制造工艺不相容。在这里,我们演示了一种完全兼容的QMOS制造方法,并显示了与最先进的约瑟夫森接线设备具有较长连贯性和松弛时间的重叠结合设备的结果。我们通过实验验证了Argon Milling(连接处制造过程中的关键步骤)以及减法蚀刻过程,但导致Qubits的平均量子能量松弛时间T1达到70 $μ$ S,最大值超过100 $μ$ s。此外,我们表明我们的结果仍然受到表面损失的限制,而不是至关重要的,而不是连接损失。因此,提出的制造工艺预示着一种重要的里程碑,用于制造300毫米CMOS工艺,以实现高稳态超导码头,并有可能提高超导设备架构的缩放。

As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become apparent. To benefit from the advanced process control in industry-scale CMOS fabrication facilities, different processing methods will be required. In particular, the double-angle evaporation and lift-off techniques used for current, state-of-the art superconducting qubits are generally incompatible with modern day manufacturable processes. Here, we demonstrate a fully CMOS compatible qubit fabrication method, and show results from overlap Josephson junction devices with long coherence and relaxation times, on par with the state-of-the-art. We experimentally verify that Argon milling - the critical step during junction fabrication - and a subtractive etch process nevertheless result in qubits with average qubit energy relaxation times T1 reaching 70 $μ$s, with maximum values exceeding 100 $μ$s. Furthermore, we show that our results are still limited by surface losses and not, crucially, by junction losses. The presented fabrication process therefore heralds an important milestone towards a manufacturable 300 mm CMOS process for high-coherence superconducting qubits and has the potential to advance the scaling of superconducting device architectures.

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