论文标题
部分可观测时空混沌系统的无模型预测
Neural-Network Decoders for Quantum Error Correction using Surface Codes:A Space Exploration of the Hardware Cost-Performance Trade-Offs
论文作者
论文摘要
量子误差校正（QEC）是量子计算机中需要的，以减轻误差对物理QUBIT的影响。在基于表面代码的QEC方案时，错误解码是经典电子后端中计算上最昂贵的任务。采用神经网络（NN）的解码器非常适合此任务，但尚未介绍其硬件实现。这项工作为针对小距离表面代码的完全连接的馈电NN解码器提供了空间探索。目的是优化神经网络以进行高解码性能，同时保持简约的硬件实现。这是满足实时表面代码解码的严格延迟约束所需的。我们证明，基于硬件的NN码编码器可以实现与其他最先进的解码算法相媲美的高度解码性能，而远低于紧密延迟要求$（\ \ \ \ \ \ \\ Mathrm {ns}）$的当前固态QUBIT技术的$（这两种ASIC DEENSIONS $（<30 \ 30 \ ns） \ mathrm {ns}）$。这些结果将NN二十码器表示为未来大型量子计算机中集成硬件实现的候选者。
Quantum Error Correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully-connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the neural network for high decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware based NN-decoders can achieve high decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements $(\approx 440\ \mathrm{ns})$ of current solid-state qubit technologies for both ASIC designs $(<30\ \mathrm{ns})$ and FPGA implementations $(<90\ \mathrm{ns})$. These results designates NN-decoders as fitting candidates for an integrated hardware implementation in future large-scale quantum computers.
