论文标题
HW/SW共同设计，用于可靠的基于TCAM的内存中脑启发的高维度计算
HW/SW Co-design for Reliable TCAM-based In-memory Brain-inspired Hyperdimensional Computing
论文作者
论文摘要
脑启发的高维计算（HDC）一直引起极大的关注。这是传统机器学习方法的一种有希望的替代方法，因为它能够从很少的数据，轻巧的实现和抵御错误的弹性中学习。但是，与传统的机器学习算法相似，HDC以数据为中心以数据为中心。内存计算正在迅速出现，以通过消除计算和存储单元之间的数据运动来克服von Neumann瓶颈。在这项工作中，我们研究并模拟了不精确的内存计算硬件对HDC推理精度的影响。我们的建模基于14nm FinFET技术，通过英特尔测量数据完全校准。我们首次准确地对基于SRAM和基于FEFET的内存中计算的电压依赖性误差概率进行建模。得益于HDC抵御错误的弹性，可以降低基础硬件的复杂性，从而可节省大量6倍。 SRAM的实验结果表明，可变性引起的错误的概率高达39％。尽管误差概率如此之高，但推断精度仅受到略有影响。这打开了探索新的权衡的大门。我们还证明，针对错误的弹性依赖于应用程序。此外，当使用新兴的非挥发性FeFET设备而不是基于成熟的CMOS的SRAM实现基础内存中的内存硬件时，我们研究了HDC对错误的鲁棒性。我们证明，尽管误差概率较大，但推理精度确实仍然很高，而可以获得大面积和功率。总而言之，HW/SW共同设计是常规CMOS技术和即将到来的新兴技术的有效但可靠的内存性高度计算的关键。
Brain-inspired hyperdimensional computing (HDC) is continuously gaining remarkable attention. It is a promising alternative to traditional machine-learning approaches due to its ability to learn from little data, lightweight implementation, and resiliency against errors. However, HDC is overwhelmingly data-centric similar to traditional machine-learning algorithms. In-memory computing is rapidly emerging to overcome the von Neumann bottleneck by eliminating data movements between compute and storage units. In this work, we investigate and model the impact of imprecise in-memory computing hardware on the inference accuracy of HDC. Our modeling is based on 14nm FinFET technology fully calibrated with Intel measurement data. We accurately model, for the first time, the voltage-dependent error probability in SRAM-based and FeFET-based in-memory computing. Thanks to HDC's resiliency against errors, the complexity of the underlying hardware can be reduced, providing large energy savings of up to 6x. Experimental results for SRAM reveal that variability-induced errors have a probability of up to 39 percent. Despite such a high error probability, the inference accuracy is only marginally impacted. This opens doors to explore new tradeoffs. We also demonstrate that the resiliency against errors is application-dependent. In addition, we investigate the robustness of HDC against errors when the underlying in-memory hardware is realized using emerging non-volatile FeFET devices instead of mature CMOS-based SRAMs. We demonstrate that inference accuracy does remain high despite the larger error probability, while large area and power savings can be obtained. All in all, HW/SW co-design is the key for efficient yet reliable in-memory hyperdimensional computing for both conventional CMOS technology and upcoming emerging technologies.
