论文标题
$β$ -GA $ _2 $ o $ $ _3 $ FET的温度依赖性当前分散研究使用子脉动脉冲iv特征
Temperature Dependent Current Dispersion Study in $β$-Ga$_2$O$_3$ FETs Using Sub-Microsecond Pulsed IV Characteristics
论文作者
论文摘要
对$β$ -GA $ _2 $ o $ $ _3 $ FETS中排水电流分散效应的全面研究已使用直流，脉冲和RF测量完成。栅极访问区域中的虚拟门效应和栅极下的界面陷阱都是实验观察到的脉冲电流分散和高温阈值电压移动的最合理的解释。由于门滞后效应的特征在于400〜 $μs$至600〜 $μs$的范围内，因此未通电的设备显示DC和脉冲IV响应之间的明显电流分散体。从温度依赖性的Arrhenius图估计，激活能量为99〜 $ MEV $。与观察到的浅陷阱水平结合使用的可变范围跳跃的慢速传输归因于观察到的漏极电流相对于时间的缓慢瞬态响应。装置制造过程中的反应离子蚀刻步骤很可能导致引入陷阱。可以通过使用表面钝化层最小化陷阱的效果，在这种情况下，氮化硅在当前的分散体和RF截止频率方面显示出显着改善。这项工作证明了陷阱对当前色散的有害效果，这显着限制了设备的高频操作。
A comprehensive study of drain current dispersion effects in $β$-Ga$_2$O$_3$ FETs has been done using DC, pulsed and RF measurements. Both virtual gate effect in the gate-drain access region and interface traps under the gate are most plausible explanations for the experimentally observed pulsed current dispersion and high temperature threshold voltage shift respectively. Unpassivated devices show significant current dispersion between DC and pulsed IV response due to gate lag effect characterized by time constants in the range of 400~$μs$ to 600~$μs$. An activation energy of 99~$meV$ is estimated from temperature dependent Arrhenius plots. A variable range hopping based slow transport in conjunction with the observed shallow trap level is attributed to the observed slow transient response of drain current with respect to time. Reactive ion etching step during the device fabrication is most likely responsible for introducing the traps. Effect of traps can be minimized by using surface passivation layers, in this case, Silicon Nitride which shows significant improvement in the current dispersion and RF cutoff frequency. This work demonstrates the detrimental effect the traps can have on the current dispersion which significantly limits the high frequency operation of the device.
