论文标题
硬件复杂性意识到设计策略，用于融合对数和反对不动的转换器
Hardware Complexity Aware Design Strategy for a Fused Logarithmic and Anti-Logarithmic Converter
论文作者
论文摘要
对数和反量化转换器是通过分段线性近似方法实现的，该方法由移位和ADD体系结构实现。该简介利用了日志和antilog函数的相似性，因此可以通过日志和antilog转换器共享加法树块和多路复用器块。结果，对数转换器可以以额外的14％面积和6％的延迟来实现Antilog函数。这意味着换档架构可以以略有硬件成本近似多个类似的非线性功能。此外，本简介提出了一组公式，以预测具有不同量化系数的移位和添加体系结构的潜伏期和潜伏期，这些系数可以促进在潜伏期区域前置空间中找到权衡点。
The logarithmic and anti-logarithmic converters are realized with the piecewise linear approximation method, which is implemented by the shift-and-add architecture. This brief utilizes the similarities of Log and Antilog functions so that the adder tree block and multiplexer block can be shared by the Log and Antilog converters. As a result, the Antilog function can be implemented by the Log converter at the cost of additional 14% area and 6% latency. It implies the shift-and-add architecture can approximate multiple similar nonlinear functions with a slightly hardware cost. In addition, this brief proposes a set of formulas to predict the area and latency of shift-and-add architecture with different quantized coefficients that can facilitate the finding of a trade-off point in the Latency-Area-Precision space.
