论文标题

开发用于SFQ大规模集成数字电路的多层制造过程

Development of Multi-Layer Fabrication Process for SFQ Large Scale Integrated Digital Circuits

论文作者

Ying, Liliang, Zhang, Xue, Niu, Minghui, Ren, Jie, Peng, Wei, Meazawa, Masaaki, Wang, Zhen

论文摘要

我们已经开发了一种制造技术,用于开发使用基于NB的Josephson连接的大型超导电路。具有10个面罩水平的标准制造工艺使用四个金属层,包括3个NB超导层和一个MO电阻层。沉积参数对膜应力,电性能和表面粗糙度的影响进行了系统的研究。高质量的NB,AL,MO和SIO2膜成功沉积了随后的电路制造。电路制造始于以目标板电阻RSH为2 OME的MO电阻器,随后是约瑟夫森结的沉积。目标临界电流密度JC设置为每CM2 6 ka。在制造过程中,用磁力过程对照监测器(PCM)模式对膜的厚度和蚀刻深度进行了监测。

We have developed a fabrication technology for the development of large-scale superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels uses four metal layers including 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2 films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 2 Ome, followed by the deposition of Josephson-junction. The target critical current density Jc was set at 6 kA per cm2. The thicknesses and etch depths of the films were monitored during fabrication with on-wafer process-control-monitor (PCM) patterns for all the wafers.

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