论文标题

Alice Inner Tracking系统读数单元上Proasic3的远程配置

Remote Configuration of the ProASIC3 on the ALICE Inner Tracking System Readout Unit

论文作者

Yuan, Shiming, Alme, Johan, Röhrich, Dieter, Richter, Matthias, Ersdal, Magnus Rentsch, Giubilato, Piero, Rinella, Gianluca Aglieri, Velure, Arild, Lupi, Matteo, Schambach, Johann Joachim

论文摘要

大型离子对撞机实验(Alice)是在CERN大型强子对撞机(LHC)进行的四个主要实验之一。爱丽丝探测器目前正在LHC即将进行的3次运行3升级。新的内部跟踪系统(ITS)子检测器是此升级的一部分。它的前端电子设备由安装在辐射环境中的192个读取单元组成。在其读数中使用的基于SRAM的Xilinx Kintex Ultrascale FPGA中的单个事件UPSETS(SEUS)表示真正关注的问题。为了清除影响Kintex配置内存的SEU,使用了基于二次闪光灯的Microsemi Proasic3e(PA3)FPGA。该设备在持续数据摄取时配置并连续磨砂Xilinx FPGA,这避免了SEU的积累。 RUS的通信路径是通过100 m长的光学链路上的辐射硬千兆收发器(GBT)系统。使用专用的JTAG总线驾驶通道,可以通过GBT慢速控制适配器(GBT-SCA)ASIC到达PA3。在运行3的过程中,可以预见的是,PA3的FPGA设计将需要升级以纠正可能的问题并添加新功能。因此,必须远程配置PA3本身,需要专用的软件工具。本文介绍了分布式工具的设计和实施,以远程重新配置PA3 FPGA。

A Large Ion Collider Experiment (ALICE) is one of the four major experiments conducted at the CERN Large Hadron Collider (LHC). The ALICE detector is currently undergoing an upgrade for the upcoming Run 3 at the LHC. The new Inner Tracking System (ITS) sub-detector is part of this upgrade. The front-end electronics of the ITS is composed by 192 Readout Units, installed in a radiation environment. Single Event Upsets (SEUs) in the SRAM-based Xilinx Kintex Ultrascale FPGAs used in the ITS readout represent a real concern. To clear SEUs affecting the Kintex configuration memory, a secondary Flash-based Microsemi ProASIC3E (PA3) FPGA is used. This device configures and continuously scrubs the Xilinx FPGA while data-taking is ongoing, which avoids accumulation of SEUs. The communication path to the RUs is via the radiation hard Gigabit Transceiver (GBT) system on 100 m long optical links. The PA3 is reachable via the GBT Slow Control Adapter (GBT-SCA) ASIC using a dedicated JTAG bus driving channel. During the course of Run 3, it is foreseeable that the FPGA design of the PA3 will require upgrades to correct possible issues and add new functionality. It is therefore mandatory that the PA3 itself can be configured remotely, for which a dedicated software tool is needed. This paper presents the design and implementation of the distributed tools to re-configure remotely the PA3 FPGAs.

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