论文标题
$μ$ NAS：微控制器的受限神经架构搜索
$μ$NAS: Constrained Neural Architecture Search for Microcontrollers
论文作者
论文摘要
物联网设备由微控制器单元（MCUS）提供动力，这是非常资源的筛分：典型的MCU可能具有功能不足的处理器，并且约为64 kb的内存和持久存储，这是计算资源的数量级，而不是深度学习所需的数量级。为这样一个平台设计神经网络需要在保持高预测性能（准确性）的同时达到低内存，存储使用和推理延迟之间取得复杂的平衡。手动实现这是极具挑战性的，因此在这项工作中，我们构建了称为$μ$ NAS的神经体系结构搜索（NAS）系统，以自动化如此省力的MCU级网络的设计。 $μ$ NAS明确针对MCUS资源稀缺的三个主要方面：RAM的大小，持久存储和处理器速度。 $μ$ NAS代表了资源有效模型的重大进步，尤其是对于“中层” MCU，内存需求范围为0.5 kb至64 kb。我们表明，在各种图像分类数据集上，$μ$ nas能够（a）将TOP-1分类精度提高4.8％，或（b）将记忆足迹降低4--13X，或（c）与现有MCU专业文献和资源效果相比，至少减少了2X的多含用操作数量。
IoT devices are powered by microcontroller units (MCUs) which are extremely resource-scarce: a typical MCU may have an underpowered processor and around 64 KB of memory and persistent storage, which is orders of magnitude fewer computational resources than is typically required for deep learning. Designing neural networks for such a platform requires an intricate balance between keeping high predictive performance (accuracy) while achieving low memory and storage usage and inference latency. This is extremely challenging to achieve manually, so in this work, we build a neural architecture search (NAS) system, called $μ$NAS, to automate the design of such small-yet-powerful MCU-level networks. $μ$NAS explicitly targets the three primary aspects of resource scarcity of MCUs: the size of RAM, persistent storage and processor speed. $μ$NAS represents a significant advance in resource-efficient models, especially for "mid-tier" MCUs with memory requirements ranging from 0.5 KB to 64 KB. We show that on a variety of image classification datasets $μ$NAS is able to (a) improve top-1 classification accuracy by up to 4.8%, or (b) reduce memory footprint by 4--13x, or (c) reduce the number of multiply-accumulate operations by at least 2x, compared to existing MCU specialist literature and resource-efficient models.
