论文标题
共振能量回收SRAM架构
Resonant Energy Recycling SRAM Architecture
论文作者
论文摘要
尽管我们可能正处于摩尔定律的末尾，但降低芯片功耗仍然是设计师的主要驱动力。为了实现低功率操作，我们提出了一个共振能量回收静态随机访问存储器（SRAM）。我们提出了第一个系列共振方案，以减少SRAM操作的动态功耗。此外，我们确定了对写缓冲区的供应提升的要求，以进行适当的谐振操作。我们使用香料和测试芯片评估了共振144KB SRAM CACE，并使用商业28NM CMOS技术进行了测试。实验结果表明，与最先进的设计相比，在1GHz操作频率下，共振剂SRAM可以节省30％的动态功率。
Although we may be at the end of Moore's law, lowering chip power consumption is still the primary driving force for the designers. To enable low-power operation, we propose a resonant energy recovery static random access memory (SRAM). We propose the first series resonance scheme to reduce the dynamic power consumption of the SRAM operation. Besides, we identified the requirement of supply boosting of the write buffers for proper resonant operation. We evaluated the resonant 144KB SRAM cache through SPICE and test chip using a commercial 28nm CMOS technology. The experimental results show that the resonant SRAM can save up to 30% dynamic power at 1GHz operating frequency compared to the state-of-the-art design.
