论文标题
逻辑锁定的建模技术
Modeling Techniques for Logic Locking
论文作者
论文摘要
逻辑锁定是一种防止知识产权（IP）盗版的方法。但是，在合理的攻击模型下，基于SAT的方法已被证明在获取秘密密钥方面具有强大的功能。作为响应，已经开发出许多锁定技术来专门抵抗这种攻击形式。在本文中，我们演示了两种SAT建模技术，可以在发现正确的钥匙时提供许多数量级的速度。具体而言，我们考虑放松的编码和对称性破坏。为了证明其影响，我们对最先进的逻辑锁定技术（全锁）进行建模和攻击。我们表明，可以在几秒钟内解决以前在运行时间后15天内无法破坏的电路。因此，在评估任何给定锁定的强度时，必须考虑这些建模技术。为了在被考虑的锁定技术中纠正这种漏洞，我们演示了扩展版本，即逻辑增强的榕树锁定，这对我们提出的建模技术具有抵抗力。
Logic locking is a method to prevent intellectual property (IP) piracy. However, under a reasonable attack model, SAT-based methods have proven to be powerful in obtaining the secret key. In response, many locking techniques have been developed to specifically resist this form of attack. In this paper, we demonstrate two SAT modeling techniques that can provide many orders of magnitude speed up in discovering the correct key. Specifically, we consider relaxed encodings and symmetry breaking. To demonstrate their impact, we model and attack a state-of-the-art logic locking technique, Full-Lock. We show that circuits previously unbreakable within 15 days of run time can be solved in seconds. Consequently, in assessing the strength of any given locking, it is imperative that these modeling techniques be considered. To remedy this vulnerability in the considered locking technique, we demonstrate an extended version, logic-enhanced Banyan locking, that is resistant to our proposed modeling techniques.
