论文标题
大型机器类型通信飞行员跳跃序列检测架构基于非负平方的无授予随机访问
Massive Machine Type Communication Pilot-Hopping Sequence Detection Architectures Based on Non-Negative Least Squares for Grant-Free Random Access
论文作者
论文摘要
使用试点跳跃序列的无授予随机访问大量机器类型通信(MMTC)中的用户活动检测可以提出为解决非负平方(NNLS)问题。在这项工作中,提出了两个使用不同算法来解决NNLS问题的体系结构。这些算法是使用完全平行的方法和固定点算术实现的,从而导致高检测率和低功耗。第一种算法(快速投射梯度)收敛到最佳值。第二算法是乘法更新,部分在对数域中实现,并提供较小的芯片区域和较低的功耗。对于每秒检测率约为100万个检测率,快速算法的芯片面积约为0.7毫米$^2 $,而在28 nm FD-SOI标准单元格过程中实现在1 V电源电源电源电压下,多用算法的乘积算法约为0.5毫米$^2 $。使用256个迭代的快速投影梯度算法的能源消耗约为300 NJ/检测,导致收敛接近理论。使用128次迭代,需要大约250 NJ/检测,检测性能在标准杆上与192个乘务算法的迭代需要大约100 NJ/检测。
User activity detection in grant-free random access massive machine type communication (mMTC) using pilot-hopping sequences can be formulated as solving a non-negative least squares (NNLS) problem. In this work, two architectures using different algorithms to solve the NNLS problem is proposed. The algorithms are implemented using a fully parallel approach and fixed-point arithmetic, leading to high detection rates and low power consumption. The first algorithm, fast projected gradients, converges faster to the optimal value. The second algorithm, multiplicative updates, is partially implemented in the logarithmic domain, and provides a smaller chip area and lower power consumption. For a detection rate of about one million detections per second, the chip area for the fast algorithm is about 0.7 mm$^2$ compared to about 0.5 mm$^2$ for the multiplicative algorithm when implemented in a 28 nm FD-SOI standard cell process at 1 V power supply voltage. The energy consumption is about 300 nJ/detection for the fast projected gradient algorithm using 256 iterations, leading to a convergence close to the theoretical. With 128 iterations, about 250 nJ/detection is required, with a detection performance on par with 192 iterations of the multiplicative algorithm for which about 100 nJ/detection is required.