论文标题
通过受控的S门进行了非克利福德交织的随机基准测试的实验实现
Experimental implementation of non-Clifford interleaved randomized benchmarking with a controlled-S gate
论文作者
论文摘要
将量子电路的硬件有效转渗透到量子设备本机门口对于在嘈杂的量子计算机上执行量子算法至关重要。典型的量子设备利用一个带有单个两倍克利福德纠缠栅极的登机馆，每对耦合量子台，但是，在某些应用程序中，在某些应用中访问非clifford二Quition栅极可能会导致更优化的电路分解，并且还可以使更具灵活性在优化过度噪声时更具灵活性。我们证明了使用Qiskit Pulse Framework在基于云的IBM量子计算上，在基于云的IBM量子计算上进行了低误差非误差的校准 - $ \fracπ{2} $ apeas（cs）门。为了测量校准的CS门的门误差，我们执行非cnot二二二二月进行了交织的随机基准测试。我们能够在门长263 ns处获得$ 5.9（7）\ times 10^{ - 3} $的门误差，该ns接近相关量子的相干限制，而误差则比后端标准校准的CNOT门较低。
Hardware efficient transpilation of quantum circuits to a quantum devices native gateset is essential for the execution of quantum algorithms on noisy quantum computers. Typical quantum devices utilize a gateset with a single two-qubit Clifford entangling gate per pair of coupled qubits, however, in some applications access to a non-Clifford two-qubit gate can result in more optimal circuit decompositions and also allows more flexibility in optimizing over noise. We demonstrate calibration of a low error non-Clifford Controlled-$\fracπ{2}$ phase (CS) gate on a cloud based IBM Quantum computing using the Qiskit Pulse framework. To measure the gate error of the calibrated CS gate we perform non-Clifford CNOT-Dihedral interleaved randomized benchmarking. We are able to obtain a gate error of $5.9(7) \times 10^{-3}$ at a gate length 263 ns, which is close to the coherence limit of the associated qubits, and lower error than the backends standard calibrated CNOT gate.
