论文标题
神经形态电路的紧凑型门伴侣模型
A Compact Gated-Synapse Model for Neuromorphic Circuits
论文作者
论文摘要
这项工作报告了一个紧凑的行为模型，用于封闭突触记忆。该模型是在Verilog-A中开发的，可轻松地将新兴记忆的计算机辅助设计集成到神经形态电路的设计中。该模型包含单个框架内的各种形式的门控突触，并且不仅限于单一类型。该模型的行为理论以及默认参数设置的完整列表进行了详细描述。该模型包括参数，例如设备的理想设定时间，阈值电压，电导相对于时间的一般演变，设备状态的衰减等。最后，该模型的有效性是通过广泛的模拟和对已发表的Gated-synaps的实验报道的数据显示的。
This work reports a compact behavioral model for gated-synaptic memory. The model is developed in Verilog-A for easy integration into computer-aided design of neuromorphic circuits using emerging memory. The model encompasses various forms of gated synapses within a single framework and is not restricted to only a single type. The behavioral theory of the model is described in detail along with a full list of the default parameter settings. The model includes parameters such as a device's ideal set time, threshold voltage, general evolution of the conductance with respect to time, decay of the device's state, etc. Finally, the model's validity is shown via extensive simulation and fitting to experimentally reported data on published gated-synapses.
