论文标题
部分可观测时空混沌系统的无模型预测
A Unified Hardware Architecture for Convolutions and Deconvolutions in CNN
论文作者
论文摘要
In this paper, a scalable neural network hardware architecture for image segmentation is proposed. By sharing the same computing resources, both convolution and deconvolution operations are handled by the same process element array. In addition, access to on-chip and off-chip memories is optimized to alleviate the burden introduced by partial sum.例如，通过针对Xilinx ZC706 FPGA来实现SEGNET-BASIC，它分别实现了Xilinx ZC706 FPGA，分别实现了151.5 GOPS和94.3 GOPS的性能，用于卷积和反向卷积。 This unified convolution/deconvolution design is applicable to other CNNs with deconvolution.
In this paper, a scalable neural network hardware architecture for image segmentation is proposed. By sharing the same computing resources, both convolution and deconvolution operations are handled by the same process element array. In addition, access to on-chip and off-chip memories is optimized to alleviate the burden introduced by partial sum. As an example, SegNet-Basic has been implemented using the proposed unified architecture by targeting on Xilinx ZC706 FPGA, which achieves the performance of 151.5 GOPS and 94.3 GOPS for convolution and deconvolution respectively. This unified convolution/deconvolution design is applicable to other CNNs with deconvolution.
