论文标题
在有电路逆向工程错误的情况下，基于可满足的攻击的功效
Efficacy of Satisfiability Based Attacks in the Presence of Circuit Reverse Engineering Errors
论文作者
论文摘要
知识产权（IP）盗窃是集成电路（IC）行业的严重关注。为了解决这一问题，逻辑锁定对策将逻辑电路转换为另一个逻辑电路，以使其内部细节混淆。仅在应用程序的秘密键时，由混淆引起的转换逆转，从而保留电路的原始功能。已知该技术容易受到满意度（SAT）的攻击。但是，为了成功，基于SAT的攻击隐含地假设了一个完全反向工程的电路，由于自动电路提取引起的反向工程（RE）错误在实践中很难实现。在本文中，我们分析了随机电路重新解释对基于SAT的攻击成功的影响。对ISCAS，MCNC基准以及成熟的RISC-V CPU的经验评估表明，随机重新纠正的数量增加，攻击成功呈指数增长。因此，对手要么必须为重新装备近乎完美地装备，要么提出更好的基于SAT的攻击，以便可以与重新配置一起使用。
Intellectual Property (IP) theft is a serious concern for the integrated circuit (IC) industry. To address this concern, logic locking countermeasure transforms a logic circuit to a different one to obfuscate its inner details. The transformation caused by obfuscation is reversed only upon application of the programmed secret key, thus preserving the circuit's original function. This technique is known to be vulnerable to Satisfiability (SAT)-based attacks. But in order to succeed, SAT-based attacks implicitly assume a perfectly reverse-engineered circuit, which is difficult to achieve in practice due to reverse engineering (RE) errors caused by automated circuit extraction. In this paper, we analyze the effects of random circuit RE-errors on the success of SAT-based attacks. Empirical evaluation on ISCAS, MCNC benchmarks as well as a fully-fledged RISC-V CPU reveals that the attack success degrades exponentially with increase in the number of random RE-errors. Therefore, the adversaries either have to equip RE-tools with near perfection or propose better SAT-based attacks that can work with RE-imperfections.
