论文标题
带有二进制翻译的多核RISC-V系统的加速周期级全系统模拟
Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation
论文作者
论文摘要
平衡ISS的准确性和性能一直很困难。 RTL模拟器或诸如GEM5之类的系统用于以周期精确的方式执行程序，但通常会过慢地执行程序。相比之下，诸如QEMU之类的功能模拟器可以在合理的时间内运行大型基准测试，但捕获很少的性能指标，并且无法建模多个内核之间的复杂相互作用。 本文提出了一种新型的多用途模拟器，该模拟器利用二进制翻译以提供快速的循环级全系统模拟。它的功能仿真模式优于QEMU，如果需要，可以在运行时在功能和时序模式之间切换。 RISC-V多核处理器的周期级模拟在20多个MIPS以上是可能的，这是一个有用的中间立场，在仿真速度的速度近100倍的中间基础上，近100倍的循环循环精确模型。
It has always been difficult to balance the accuracy and performance of ISSs. RTL simulators or systems such as gem5 are used to execute programs in a cycle-accurate manner but are often prohibitively slow. In contrast, functional simulators such as QEMU can run large benchmarks to completion in a reasonable time yet capture few performance metrics and fail to model complex interactions between multiple cores. This paper presents a novel multi-purpose simulator that exploits binary translation to offer fast cycle-level full-system simulations. Its functional simulation mode outperforms QEMU and, if desired, it is possible to switch between functional and timing modes at run-time. Cycle-level simulations of RISC-V multi-core processors are possible at more than 20 MIPS, a useful middle ground in terms of accuracy and performance with simulation speeds nearly 100 times those of more detailed cycle-accurate models.
