论文标题
堆叠您的芯片：押注3D集成以增强摩尔定律的扩展
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling
论文作者
论文摘要
3D集成，即使用并行或顺序处理的集成电路层堆叠，随着Moore定律规模的放缓，正在迅速采用行业。 3D堆叠有望在性能，功率和成本上的潜在增长，但实际收益的实际幅度取决于最终应用，技术选择和设计。在这次演讲中，我们将讨论与3D设计相关的一些关键挑战，以及3D设计将如何要求我们打破传统的微体系结构，电路/物理设计和制造技术的孤岛，以跨抽象来工作，以实现3D技术承诺的收益。
3D integration, i.e., stacking of integrated circuit layers using parallel or sequential processing is gaining rapid industry adoption with the slowdown of Moore's law scaling. 3D stacking promises potential gains in performance, power and cost but the actual magnitude of gains varies depending on end-application, technology choices and design. In this talk, we will discuss some key challenges associated with 3D design and how design-for-3D will require us to break traditional silos of micro-architecture, circuit/physical design and manufacturing technology to work across abstractions to enable the gains promised by 3D technologies.
