论文标题
比较第四纪和二进制乘数
Comparing quaternary and binary multipliers
论文作者
论文摘要
我们比较了8x8位乘数的实现与4x4 Quaternary Digit乘数的两个不同的实现。将此二进制乘数与二进制解码器和二进制编码器与二进制编码器进行连接导致4x4乘法器，从而优于4x4 Quaternary乘数的最佳直接实现。与二进制1位乘数和完整添加程序相比，该直接实施中使用的1位乘数和1位添加器的复杂性更大，无法通过减少的第四纪运营商计数来补偿。由于最佳的四元乘数包括相应的二进制文件，这意味着没有机会获得更少的互连，芯片较少的区域，与第四纪乘数的功率耗散较小。
We compare the implementation of a 8x8 bit multiplier with two different implementations of a 4x4 quaternary digit multiplier. Interfacing this binary multiplier with quaternary to binary decoders and binary to quaternary encoders leads to a 4x4 multiplier that outperforms the best direct implementation of a 4x4 quaternary multiplier. The far greater complexity of the 1-digit multipliers and 1-digit adders used in this direct implementation compared to the binary 1-bit multipliers and full adders cannot be compensated by the reduced count of quaternary operators. As the best quaternary multiplier includes the corresponding binary one, it means that there is no opportunity to get less interconnects, less chip area, less power dissipation with the quaternary multiplier.
