论文标题
PMEVO：通过进化优化的端口映射推理端口映射的推理
PMEvo: Portable Inference of Port Mappings for Out-of-Order Processors by Evolutionary Optimization
论文作者
论文摘要
在计算机系统中实现峰值性能需要在系统的各个层中进行优化，无论是硬件还是软件。对基础硬件，尤其是处理器的详细理解对于优化软件至关重要。处理器性能的一个关键标准是其利用指令级并行性的能力。此功能由处理器的端口映射确定，该端口映射描述了每个指令的处理器的执行单元。 处理器制造商通常不共享其微体系构造的端口映射。尽管存在从实验中自动推断端口映射的方法，但它们基于每个平台上不可用的处理器特定的硬件性能计数器。 我们提出PMEVO，这是一个仅基于简短指令序列的执行时间的测量，可以自动推断端口映射的框架。 PMEVO使用一种进化算法，该算法评估候选映射的适用性，其分析吞吐量模型以线性程序为例。我们的原型实施侵犯了英特尔Skylake架构的端口映射，该端口映射可预测测量的指导吞吐量，其准确性与现有工作具有竞争力。此外，它找到了AMD的Zen+架构和ARM Cortex-A72体系结构的端口映射，这些体系结构不在现有技术的范围之内。
Achieving peak performance in a computer system requires optimizations in every layer of the system, be it hardware or software. A detailed understanding of the underlying hardware, and especially the processor, is crucial to optimize software. One key criterion for the performance of a processor is its ability to exploit instruction-level parallelism. This ability is determined by the port mapping of the processor, which describes the execution units of the processor for each instruction. Processor manufacturers usually do not share the port mappings of their microarchitectures. While approaches to automatically infer port mappings from experiments exist, they are based on processor-specific hardware performance counters that are not available on every platform. We present PMEvo, a framework to automatically infer port mappings solely based on the measurement of the execution time of short instruction sequences. PMEvo uses an evolutionary algorithm that evaluates the fitness of candidate mappings with an analytical throughput model formulated as a linear program. Our prototype implementation infers a port mapping for Intel's Skylake architecture that predicts measured instruction throughput with an accuracy that is competitive to existing work. Furthermore, it finds port mappings for AMD's Zen+ architecture and the ARM Cortex-A72 architecture, which are out of scope of existing techniques.
