论文标题
模式锁定的激光正时正时抖动限制在光学启用,光谱切成薄片的ADC中
Mode-locked laser timing jitter limitation in optically enabled, spectrally sliced ADCs
论文作者
论文摘要
新颖的模数转换器(ADC)架构是出于对采样率上升速率和有效数量(ENOB)的需求的动机。纯电气ADC中应附于试要的主要局限性在于相对较高的振荡器抖动,以几十个FS的速度用于最先进的组件。与在Attosecond范围内使用一流的Ti:蓝宝石模式锁定激光器(MLL)获得的极低抖动相比,很明显,混合的电光体系结构可以显着改善转换器的应附器。在讨论了系统体系结构和实现细节后,我们在光学启用,光谱切片的ADC中对轴承源建模和分析。光载体的相位噪声(用于电信信号转导的服务)被证明不传播到重建的数字化信号,因此不代表基本限制。只要所有梳子线之间保持相关性,用于生成单个切片的参考音调的MLL的光相噪声也不会从根本上影响转换的信号。另一方面,MLL的定时抖动,以及其RF线宽的反映,从根本上限制了ADC性能,因为它被直接映射到转换信号。光子启用的杂种性质,频谱切成薄片的ADC意味着利用许多还原的带宽电气ADC转换平行切片,从而导致电振荡器从提供其时钟的电振荡器传播抖动。由于电气ADC的采样率降低,与整体系统相比,相对于完全电气ADC,提出的结构的总体噪声性能大大提高。
Novel analog-to-digital converter (ADC) architectures are motivated by the demand for rising sampling rates and effective number of bits (ENOB). The main limitation on ENOB in purely electrical ADCs lies in the relatively high jitter of oscillators, in the order of a few tens of fs for state-of-the-art components. When compared to the extremely low jitter obtained with best-in-class Ti:sapphire mode-locked lasers (MLL), in the attosecond range, it is apparent that a mixed electrical-optical architecture could significantly improve the converters' ENOB. We model and analyze the ENOB limitations arising from optical sources in optically enabled, spectrally sliced ADCs, after discussing the system architecture and implementation details. The phase noise of the optical carrier, serving for electro-optic signal transduction, is shown not to propagate to the reconstructed digitized signal and therefore not to represent a fundamental limit. The optical phase noise of the MLL used to generate reference tones for individual slices also does not fundamentally impact the converted signal, so long as it remains correlated among all the comb lines. On the other hand, the timing jitter of the MLL, as also reflected in its RF linewidth, is fundamentally limiting the ADC performance, since it is directly mapped as jitter to the converted signal. The hybrid nature of a photonically enabled, spectrally sliced ADC implies the utilization of a number of reduced bandwidth electrical ADCs to convert parallel slices, resulting in the propagation of jitter from the electrical oscillator supplying their clock. Due to the reduced sampling rate of the electrical ADCs, as compared to the overall system, the overall noise performance of the presented architecture is substantially improved with respect to a fully electrical ADC.