论文标题
用于神经网络训练和推理的混合动力FEMFET-CMOS模拟突触电路
A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference
论文作者
论文摘要
提出了基于铁电场现场效应晶体管的模拟突触电路，可提供6位的重量精度。该电路由仅在训练过程中使用的挥发性最低显着位（LSB）组成，而非易失性最重要的位（MSB）则包括用于训练和推理。该设计以1.8V逻辑兼容的电压起作用，提供10^10个耐力周期，仅需要250PS更新脉冲。经过拟议的突触训练的LENET变体可在MNIST上达到98.2％的精度，比相同精度的同一网络的理想实现仅比理想的实现低0.4％。此外，与最先进的混合型突触电路相比，拟议的突触可改善面积高达26％，泄漏功率为44.8％，LSB更新脉冲持续时间16.7％，耐力周期的数量级有两个数量级。我们提出的突触可以扩展到8位设计，从而使类似VGG的网络在CIFAR-10上实现88.8％的精度（仅比同一网络的理想实现低0.8％）。
An analog synapse circuit based on ferroelectric-metal field-effect transistors is proposed, that offers 6-bit weight precision. The circuit is comprised of volatile least significant bits (LSBs) used solely during training, and non-volatile most significant bits (MSBs) used for both training and inference. The design works at a 1.8V logic-compatible voltage, provides 10^10 endurance cycles, and requires only 250ps update pulses. A variant of LeNet trained with the proposed synapse achieves 98.2% accuracy on MNIST, which is only 0.4% lower than an ideal implementation of the same network with the same bit precision. Furthermore, the proposed synapse offers improvements of up to 26% in area, 44.8% in leakage power, 16.7% in LSB update pulse duration, and two orders of magnitude in endurance cycles, when compared to state-of-the-art hybrid synaptic circuits. Our proposed synapse can be extended to an 8-bit design, enabling a VGG-like network to achieve 88.8% accuracy on CIFAR-10 (only 0.8% lower than an ideal implementation of the same network).
