论文标题
Fakernet-小而快速的基于FPGA的TCP和UDP通信
Fakernet -- small and fast FPGA-based TCP and UDP communication
论文作者
论文摘要
数据采集系统的一个共同主题是将数据从数字化前端模块传输到稳定的存储和在线分析。今天的一个不错的选择是将其基于无处不在，商业和便宜的以太网技术。固件构建块已经将前端电子设备的FPGA转换为TCP数据源和UDP控制接口，并提出了UDP控制界面。总体性能目标是能够使用出站数据饱和1 GBPS网络链接，同时使用少量FPGA资源。目的是用普通以太网设备替换自定义数据总线和协议的使用。这些目标是通过恰好符合的，因此与此处呈现的Fakernet系统接口的PC设备接口不需要特殊的驱动程序。一个重要的设计选择是在内部以16位单词的形式处理所有数据包数据，从而减少了时钟速度的要求。一个有利的情况是，即使在1 Gbps的速度下，对于本地网络段，往返时间通常远低于500微秒。因此，少于50 KIB未经封闭的数据需要在飞行中，从而可以在没有TCP窗口缩放的情况下饱和网络链接。到目前为止，Fakernet系统已显示出以11.7 Mb/s的TCP输出数据饱和100 Mbps的链接，并能够以超过450 kword/s的速度进行32位控制寄存器访问。
A common theme of data acquisition systems is the transport of data from digitising front-end modules to stable storage and online analysis. A good choice today is to base this on the ubiquitous, commercially and cheaply available Ethernet technology. A firmware building block to turn already the FPGA of front-end electronics into a TCP data source and UDP control interface using a data-flow architecture is presented. The overall performance targets are to be able to saturate a 1 Gbps network link with outbound data, while using few FPGA resources. The goal is to replace the use of custom data buses and protocols with ordinary Ethernet equipment. These objectives are achieved by being just-enough conforming, such that no special drivers are needed in the PC equipment interfacing with the here presented Fakernet system. An important design choice is to handle all packet-data internally as 16-bit words, thus reducing the clock-speed requirements. An advantageous circumstance is that even at 1 Gbps speeds, for local network segments, the round-trip times are usually well below 500 microseconds. Thus, less than 50 kiB of unacknowledged data needs to be in-flight, allowing to saturate a network link without TCP window scaling. The Fakernet system has so far been shown to saturate a 100 Mbps link at 11.7 MB/s of TCP output data, and able to do 32-bit control register accesses at over 450 kword/s.
