论文标题
重新设计的光子互连与在片上通信的超低能量的硅式设备平台
Redesigning Photonic Interconnects with Silicon-on-Sapphire Device Platform for Ultra-Low-Energy On-Chip Communication
论文作者
论文摘要
基于芯片光子互连的传统硅在绝缘子（SOI）平台由于构成光子设备的光学非线性诱导功率约束，因此能量带宽可扩展性有限。在本文中，我们建议使用基于新型硅（SOS）的光子设备平台打破这种可伸缩性障碍。我们的物理层表征结果表明，基于SOS的光子设备在4μm附近的中红外区域具有可忽略的光学非线性效应，这大大减轻了其功率约束。我们的链接级分析表明，基于SOS的光子设备可用于实现具有超过1 tb/s的汇总数据速率的光子链接，最近对基于SOI的基于SOI的光子片上链路无法实现。我们还表明，这种高通量SOS的光子链路可以显着提高芯片光子通信体系结构的能源效率。我们的系统级分析结果将基于SOS的光子互连位置为实现超低能量（<1 pj/bit）的芯片数据传输铺平道路。
Traditional silicon-on-insulator (SOI) platform based on-chip photonic interconnects have limited energy-bandwidth scalability due to the optical non-linearity induced power constraints of the constituent photonic devices. In this paper, we propose to break this scalability barrier using a new silicon-on-sapphire (SOS) based photonic device platform. Our physical-layer characterization results show that SOS-based photonic devices have negligible optical non-linearity effects in the mid-infrared region near 4μm, which drastically alleviates their power constraints. Our link-level analysis shows that SOS-based photonic devices can be used to realize photonic links with aggregated data rate of more than 1 Tb/s, which recently has been deemed unattainable for the SOI-based photonic on-chip links. We also show that such high-throughput SOS-based photonic links can significantly improve the energy-efficiency of on-chip photonic communication architectures. Our system-level analysis results position SOS-based photonic interconnects to pave the way for realizing ultra-low-energy (< 1 pJ/bit) on-chip data transfers.
