论文标题
可靠的3D-NOC系统的软错误和硬故障耐受体系结构和路由算法
Soft-Error and Hard-fault Tolerant Architecture and Routing Algorithm for Reliable 3D-NoC Systems
论文作者
论文摘要
片上的网络（NOC）范式已被提议作为一种吉祥的解决方案，以应对单个多核和多核芯片上日益大量的核心之间的严格通信要求。但是，NOC系统暴露于各种制造，设计和能量颗粒因素因素，使其容易受到永久（硬）故障和瞬态（软）错误的影响。在本文中，我们提出了一个综合的软误差和硬化耐受的3D-NOC架构，称为3D-耐力 - 耐受性的耐受性oasis-noc（3d-feto）。借助自适应算法，3D-FETO能够从路由管道阶段发生的软误差中检测和恢复，并利用可重新配置的组件来处理链路，输入缓冲区和跨杆的永久性故障。深入的评估结果表明，3D-FETO系统能够解决不同类型的硬故障和软错误，同时确保优雅的性能退化，从而最大程度地减少了其他硬件复杂性并保持较低的功率。
Network-on-Chip (NoC) paradigm has been proposed as an auspicious solution to handle the strict communication requirements between the increasingly large number of cores on a single multi and many-core chips. However, NoC systems are exposed to a variety of manufacturing, design and energetic particles factors making them vulnerable to permanent (hard) faults and transient (soft) errors. In this paper, we present a comprehensive soft error and hard fault tolerant 3D-NoC architecture, named 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO). With the aid of adaptive algorithms, 3D-FETO is capable of detecting and recovering from soft errors occurring in the routing pipeline stages and is leveraging on reconfigurable components to handle permanent faults occurrence in links, input buffers, and crossbar. In-depth evaluation results show that the 3D-FETO system is able to work around different kinds of hard faults and soft errors while ensuring graceful performance degradation, minimizing the additional hardware complexity and remaining power-efficient.
