论文标题
软件软件编码适用于软件定义的无线电：IEEE 802.11p接收器案例研究
Hardware-Software Codesign for Software Defined Radio: IEEE 802.11p receiver case study
论文作者
论文摘要
软件定义的无线电（SDR）平台是设计新的无线技术或改善现有技术规范的有用工具。 IEEE 802.11p是无线车辆临时网络（VANETS）的事实上的标准。它已在GNU无线电SDR [1]上实现，该型号经历了框架解码/编码延迟。在本文中，提出了基于FPGA的SDR作为加速IEEE 802.11p波形的框架解码的解决方案。我们在设计和验证真正的基于FPGA的嵌入式硬件体系结构顶部的SDR方面分享了我们的经验。在FPGA Zynq平台的顶部，我们按照硬件/软件（HW/SW）代码码方法移植SDR GNU收音机。 SDR系统的实时分析表明，具有FFT软件功能的OFDM均衡器是整个SDR接收器功能中最耗时的任务（34.74％）。我们建议使用FPGA Zynq的免费逻辑门作为硬件（HW）加速器的FFT处理功能的硬件加速度。与纯软件实现相比，具有FFT子功能的HW OFDM均衡器可以加速SDR链的处理。我们的基于FPGA的SDR设计是提出嵌入式SDR的关键步骤。这不仅是IEEE 802.11p标准的替代方法，而且是任何基于OFDM的SDR的替代方法。
Software Defined Radio (SDR) platforms are useful tools to design new wireless technologies or to improve specifications of existing ones. The IEEE 802.11p is the de-facto standard for Wireless Vehicular Ad-hoc NETworks (VANETs). It has been implemented on GNU Radio SDR [1], which experiences frames decoding/encoding latency. In this paper an FPGA based SDR is proposed as a solution to accelerate frame decoding of IEEE 802.11p waveforms. We share our experience in designing and validating an SDR on the top of real FPGA based embedded hardware architecture. On the top of an FPGA Zynq platform, we port an SDR GNU Radio following hardware/software (HW/SW) codesign approach. A real time profiling of the SDR system shows that the OFDM equalizer with FFT software function is the most time consuming task of the whole SDR receiver functions (34.74%). We suggest hardware acceleration of the FFT processing function using the free logic gates of the FPGA Zynq as a Hardware (HW) accelerator. The HW OFDM Equalizer with FFT sub-function could accelerate the SDR chain processing in comparison with a pure software implementation. Our FPGA based SDR design is a key step toward proposing an embedded SDR. It would be an alternative for not only the IEEE 802.11p standard but for any OFDM based SDR.
