论文标题
朋友：浮光和局部同步系统
PALS: Plesiochronous and Locally Synchronous Systems
论文作者
论文摘要
考虑一个任意在芯片上通信模块的网络，每个网络都需要一个本地信号，告诉它何时执行计算步骤。生成这样的本地时钟信号有三种常见的解决方案：（i）通过单个中央时钟源派生，（ii）通过本地的，自由运行的振荡器或（iii）在相邻模块之间握手。从概念上讲，这些解决方案中的每一个都是感知到的二分法的结果，其中（子）系统是时钟或完全异步的，这表明设计师的选择仅限于决定在同步设计和异步设计之间绘制界限的位置。相比之下，我们认为更好的问题是系统可以而且应该是如何同步的。基于分布式时钟同步算法，我们提出了一种新颖的设计，该设计为模块提供了本地时钟的频率边界几乎与相应的自由运行振荡器的频率界限一样好，但是相邻的模块保证的相位偏移量大大小于一个时钟周期。具体而言，从32x32节点网格网络的相位偏移量上以2GHz的15nm ASIC实现进行了15nm ASIC实现的参数。
Consider an arbitrary network of communicating modules on a chip, each requiring a local signal telling it when to execute a computational step. There are three common solutions to generating such a local clock signal: (i) by deriving it from a single, central clock source, (ii) by local, free-running oscillators, or (iii) by handshaking between neighboring modules. Conceptually, each of these solutions is the result of a perceived dichotomy in which (sub)systems are either clocked or fully asynchronous, suggesting that the designer's choice is limited to deciding where to draw the line between synchronous and asynchronous design. In contrast, we take the view that the better question to ask is how synchronous the system can and should be. Based on a distributed clock synchronization algorithm, we present a novel design providing modules with local clocks whose frequency bounds are almost as good as those of corresponding free-running oscillators, yet neighboring modules are guaranteed to have a phase offset substantially smaller than one clock cycle. Concretely, parameters obtained from a 15nm ASIC implementation running at 2GHz yield mathematical worst-case bounds of 30ps on phase offset for a 32x32 node grid network.
