论文标题
编译用于计算记忆加速器的神经网络
Compiling Neural Networks for a Computational Memory Accelerator
论文作者
论文摘要
计算记忆（CM）是通过使用增强的记忆来加速神经网络（NN）的一种有前途的方法，而增强的记忆除了存储数据外，还允许对其进行计算。这种方法的主要挑战之一是定义一个硬件/软件接口，该界面允许编译器映射NN模型以在基础CM加速器上有效执行。这是一项非平凡的任务，因为效率表明，CM加速器被明确编程为数据流引擎，其中不同NN层的执行形成管道。在本文中，我们将工作介绍给软件堆栈，用于在这样的多核CM加速器上执行ML模型。我们描述了硬件和软件的体系结构，并专注于实现适当的控制逻辑的问题，以便尊重数据依赖性。我们提出了基于多面体汇编的后者的解决方案。
Computational memory (CM) is a promising approach for accelerating inference on neural networks (NN) by using enhanced memories that, in addition to storing data, allow computations on them. One of the main challenges of this approach is defining a hardware/software interface that allows a compiler to map NN models for efficient execution on the underlying CM accelerator. This is a non-trivial task because efficiency dictates that the CM accelerator is explicitly programmed as a dataflow engine where the execution of the different NN layers form a pipeline. In this paper, we present our work towards a software stack for executing ML models on such a multi-core CM accelerator. We describe an architecture for the hardware and software, and focus on the problem of implementing the appropriate control logic so that data dependencies are respected. We propose a solution to the latter that is based on polyhedral compilation.
