论文标题
低热预算高k/金属表面门,用于掩埋的供体设备
Low Thermal Budget High-k/Metal Surface Gate for Buried Donor-Based Devices
论文作者
论文摘要
原子精度高级制造(APAM)在掺杂固体溶解度极限的原子薄层中提供了供体设备的创建,从而实现了独特的设备物理。这为使用APAM作为探路平台的机会提供了一个机会,以根据原子限制调查数字电子产品。扩展到较小的晶体管越来越困难和昂贵,需要研究扩展到原子量表的替代制造路径。可以使用扫描隧道显微镜(STM)创建APAM供体设备。但是,这些设备目前与行业标准制造过程不兼容。在低热预算(LT)过程之间存在一个权衡,以限制掺杂剂扩散和高热预算(HT)过程,从而增加了外延SI的无缺陷层和门氧化物。为此,我们开发了与原子上精确的单电子晶体管(set)集成的LT外延SI盖和LT沉积的Al2O3门氧化物,我们用作电表来表征栅极堆栈的质量。表面门控套件表现出预期的库仑阻滞行为。但是,栅极在集合上的杠杆受到集合上方层的缺陷的限制,包括SI和氧化物之间的接口,以及Si Cap中的结构和化学缺陷。我们提出了一个更复杂的门堆栈和过程流动,预计将在未来的原子精度设备中提高性能。
Atomic precision advanced manufacturing (APAM) offers creation of donor devices in an atomically thin layer doped beyond the solid solubility limit, enabling unique device physics. This presents an opportunity to use APAM as a pathfinding platform to investigate digital electronics at the atomic limit. Scaling to smaller transistors is increasingly difficult and expensive, necessitating the investigation of alternative fabrication paths that extend to the atomic scale. APAM donor devices can be created using a scanning tunneling microscope (STM). However, these devices are not currently compatible with industry standard fabrication processes. There exists a tradeoff between low thermal budget (LT) processes to limit dopant diffusion and high thermal budget (HT) processes to grow defect-free layers of epitaxial Si and gate oxide. To this end, we have developed an LT epitaxial Si cap and LT deposited Al2O3 gate oxide integrated with an atomically precise single-electron transistor (SET) that we use as an electrometer to characterize the quality of the gate stack. The surface-gated SET exhibits the expected Coulomb blockade behavior. However, the leverage of the gate over the SET is limited by defects in the layers above the SET, including interfaces between the Si and oxide, and structural and chemical defects in the Si cap. We propose a more sophisticated gate stack and process flow that is predicted to improve performance in future atomic precision devices.