论文标题
合成紧凑型硬件以加速传感器中物理信号的推理
Synthesizing Compact Hardware for Accelerating Inference from Physical Signals in Sensors
论文作者
论文摘要
我们提出了尺寸电路合成，这是一种生成数字逻辑电路的新方法，从传感器数据提高了机器学习模型的训练效率和推断。该方法生成的硬件加速器足够紧凑（几千个大门），以允许在传感器传感器旁边的低成本微型传感器集成电路中集成。该方法作为输入在传感器转导过程中相关信号的物理属性的描述，并作为输出作为计算电路的Verilog寄存器传输级别（RTL）描述，该描述计算低级功能，该功能利用了系统中信号的度量单位。 我们将尺寸电路合成作为牛顿编译器的后端，牛顿是一种描述物理系统的语言。我们根据7个物理系统的描述评估了后端实现及其生成的硬件。结果表明，我们对尺寸电路合成的实施生成的电路仅为1662逻辑单元 / 1239门，用于我们评估的系统。 我们合成了由尺寸电路合成汇编产生的设计，该设计由其制造商在传感器接口应用程序上针对的低功率微型FPGA。该方法生成的电路仅使用2.15x2.5 mm FPGA的资源的27％。我们测量了FPGA孤立的核心电源导轨的功率耗散，并表明，通过伪随机信号输入流驱动，合成的设计使用少于1.0兆瓦，不超过5.8兆瓦。这些结果表明，在传感器传感器旁边，在低成本微型传感器集成电路中将物理启发的机器学习方法整合到低成本的传感器集成电路中的可行性。
We present dimensional circuit synthesis, a new method for generating digital logic circuits that improve the efficiency of training and inference of machine learning models from sensor data. The hardware accelerators that the method generates are compact enough (a few thousand gates) to allow integration within low-cost miniaturized sensor integrated circuits, right next to the sensor transducer. The method takes as input a description of physical properties of relevant signals in the sensor transduction process and generates as output a Verilog register transfer level (RTL) description for a circuit that computes low-level features that exploit the units of measure of the signals in the system. We implement dimensional circuit synthesis as a backend to the compiler for Newton, a language for describing physical systems. We evaluate the backend implementation and the hardware it generates, on descriptions of 7 physical systems. The results show that our implementation of dimensional circuit synthesis generates circuits of as little as 1662 logic cells / 1239 gates for the systems we evaluate. We synthesize the designs generated by the dimensional circuit synthesis compilation backend for a low-power miniature FPGA targeted by its manufacturer at sensor interface applications. The circuits which the method generated use as little as 27% of the resources of the 2.15x2.5 mm FPGA. We measure the power dissipation of the FPGA's isolated core supply rail and show that, driven with a pseudorandom signal input stream, the synthesized designs use as little as 1.0 mW and no more than 5.8 mW. These results show the feasibility of integrating physics-inspired machine learning methods within low-cost miniaturized sensor integrated circuits, right next to the sensor transducer.
